Integrated circuit (“IC”) design has many phases. One such phase is the testing/verification of the design in which the operation of the integrated circuit is simulated including, for example, simulated logic processing, signal transmission and signal reception. The timing of the integrated circuit design is also simulated. The simulation of the integrated circuit is typically performed by a computer system known as a “test bench.” The test bench also includes software for testing the operations of the simulated integrated circuit.
One focus of IC simulation is the “clock network analysis” or “clock analysis”, which simulates the propagation of the clock signal over a clock distribution network. The clock signal is used to synchronize different parts of the circuit, and cycles at a rate less than the worst-case internal propagation delays. However, as ICs become more complex, the problem of supplying accurate and synchronized clocks to all the circuits becomes increasingly difficult.
Further, the size of the typical clock distribution network has grown dramatically to hundreds of thousands of devices and greater. However, due to the accuracy requirements, the clock network analysis is typically performed using traditional transistor level circuit simulators with super-linear run time scaling with respect to the number of devices. Although these fast circuit simulators can provide a significant performance improvement over more traditional analysis, the accuracy tradeoff is generally not acceptable for clock skew analysis.